1. Field of the Invention
This invention generally relates to the field of transmission line structure, and more particularly, to a complementary-conducting-strip transmission line (thereinafter called CCS TL) structure whose capacitive region has at least one slit structure.
2. Description of the Prior Art
Recently, a literature survey shows that there has been renewed interest in the implementation of the microwave/millimeter transmission line based hybrids, which are fabricated by laminated PCB, in monolithic integrated technologies (T. Hirota, A. Minakawa, and M. Muraguchi, “Reduced-size branch-line and rat-race hybrids for uniplanar MMICs,” IEEE Trans. Microwave Theory and Tech., vol. 38, no. 3, pp. 270-275, March 1990; I. Toyoda, T. Hirota, T. Hiraoka, and T. Tokumitsu, “Multilayer MMIC branch-line coupler and broad-side coupler,” IEEE 1992 Microwave and millimeter-wave monolithic circuit symp., pp. 79-82, 1992; K. Hettak, G. A. Morin, and M. G. Stubbs, “Compact MMIC CPW and asymmetric CPS branch-Line couplers and Wilkinson dividers using shunt and series stub loading,” IEEE Trans. Microwave Theory and Tech., vol. 53, no. 5, pp. 1624-1635, May 2005; Y. Yun, “A novel microstrip-line structure employing a periodically perforated ground metal and its application to highly miniaturized and low-impedance passive components fabricated on GaAs MMIC,” IEEE Trans. Microwave Theory and Tech., vol. 53, no. 6, pp. 1951-1959, June 2005; K. Hettak, G. A. Morin, and M. G. Stubbs, “A new miniaturized type of three-dimensional SiGe 90° hybrid coupler at 20 GHz using the meandering TFMS and stripline shunt stub loading,” IEEE MTT-S Int. Microwave symp. Dig., pp. 33-36, 2007). As a result, the technologies mentioned above can easily meet the needs for size integration by applying the multilayer technology to miniaturize hybrids.
On the other hand, very little work has been reported in the course of implementing the miniaturized hybrids in standard CMOS process due to the availability of manufactured passive components with low quality-factor. The concepts of the synthetic quasi-transverse-electromagnetic (quasi-TEM) transmission line (or complementary-conducting-strip transmission line (thereinafter called CCS TL)) were recently reported, achieving low-loss and circuit miniaturization simultaneously (M. -J. Chiang, H. -S. Wu and C. -K. C. Tzuang, “Design of synthetic quasi-TEM transmission line for CMOS compact integrated circuit,” IEEE Trans. Microwave Theory and Tech., vol. 55, no. 12, part 1, pp. 2512-2520, December 2007; M. -J. Chiang, H. -S. Wu and C. -K. C. Tzuang, “A Kα-band CMOS Wilkinson power divider using synthetic quasi-TEM transmission lines,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 12, pp. 837-839, December 2007; S. Wang, H. -S. Wu, and C. -K. C. Tzuang, “Compacted Kα-band CMOS rat-race hybrid using synthesized transmission line,” IEEE MTT-S Int. Microwave symp. Dig., pp. 1023-1026, 2007). Such successes are mainly caused by efficiently meandered transmission line to achieve highest degree of integration. Furthermore, the metal density, which denote the ratio of the total metal layout area to the occupied area, is strongly required by the foundry to manage the variation of CMP in wafer manufacture, maintaining the wafer yield and design reliability (A. B. Kahng, G. Robins, A. Singh, and Zelikovsky, “New and exact filling algorithms for layout density control,” Proceedings of the 12th International Conference on VLSI Design (VLSID'99), pp. 106-110, January 1999). The foundry requires very metal layer in CMOS process to meet the minimum metal density requirement in order to maintain the wafer yield in wafer manufacture. Such process issue, which is specifically defined by the manufacture, dominated the yield of the CMOS circuit. Very recently, two on-chip transmission lines had been reported to demonstrate their realizations can be fully compatible with the standard CMOS processes and can be designed for meeting the requirements of metal density. The CMOS transmission line shows that the multilayer coplanar waveguide (thereinafter called MCPW) with the split ground plane is realized by only the two-topmost metal layers (Y. Zhu, S. Wang and H. Wu, “Multilayer coplanar waveguide transmission lines compatible with standard digital silicon technologies,” IEEE MTT-S Int. Microwave symp. Dig., 2007, pp. 1567-1570). The guiding characteristics of the MCPW can be synthesized by the width of the signal trace and the gap between two half ground planes. As shown in FIG. 3 of Y. Zhu, S. Wang and H. Wu, “Multilayer coplanar waveguide transmission lines compatible with standard digital silicon technologies, ” IEEE MTT-S Int. Microwave symp. Dig. 2007, pp. 1567-1570., the split ground plane shields the signal trace from the extra dummy metal filling, which is not included in the MCPW syntheses. The other CMOS transmission line is so-called the CCS TL (M. -J. Chiang, H. -S. Wu and C. -K. C. Tzuang, “Design of synthetic quasi-TEM transmission line for CMOS compact integrated circuit,” IEEE Trans. Microwave Theory and Tech., vol. 55, no. 12, part 1, pp. 2512-2520, December 2007). The CCS TL had been demonstrated on the CMOS components and SOC (system on chip) miniaturization. As to other monolithic integrated circuits, they need additional chip area for filling dummy metal to keep the yield of the CMOS circuit and design reliability when their metal density does not meet the manufacturing requirement. However, by following the abovementioned process, the monolithic integrated circuits cannot achieve the miniaturization.
In view of the drawbacks mentioned with the prior art of transmission line structure, there is a continuous need to develop a new and improved CCS TL structure that overcomes the shortages associated with the prior art. The advantages of the present invention are that it solves the problems mentioned above.